1. Field of the Invention
The present invention relates to display devices for displaying images, and more particularly, to a shift register for the display devices and a method of driving a transistor in the shift register.
2. Description of the Related Art
Generally, liquid crystal display devices are equipped with a gate driver integrated circuit which is mounted on a liquid crystal display panel by means of a tape carrier package (TCP) or a chip-on-glass (COG) method. The liquid crystal display devices equipped with a gate driver integrated circuit have disadvantages such as high the manufacturing cost and structural hindrance in designing a liquid crystal display device. To overcome such disadvantages, the liquid crystal display devices have been developed to employ a “gate-IC-less” structure, in which no such gate driver integrated circuit is mounted on a liquid crystal display panel. Instead, in the liquid crystal display devices with the “gate-IC-less” structure, a driving circuit using amorphous-silicon thin film transistors (a-Si TFTs) is employed to perform the substantially same function as performed by the gate driver integrated circuit.
Examples of a shift register circuit for display devices, which includes amorphous-silicon thin film transistors, are disclosed in the U.S. Pat. No. 5,517,542 and the U.S. Laid Open Publication No. 2002-0149318. The shift register circuit disclosed in the U.S. Laid Open Publication No. 2002-0149318 includes seven amorphous-silicon thin film transistors in its each stage.
FIG. 1 is a circuit diagram illustrating a stage of a conventional shift register such as one disclosed in the U.S. Laid Open Publication No. 2002-0149318, and FIG. 2 is a block diagram illustrating a shift register having multiple stages. In a display device having such shift register, the shift register replaces the gate driver integrated circuit. In other words, the shift register is integrated in a thin film transistor liquid crystal display panel to perform the same operation as the gate driver integrated circuit does.
Referring to FIGS. 1 and 2, each of the stages in the shift register includes a pull-up part 110, a pull-down part 120, a pull-up driver 130 and a pull-down driver 140. The present stage receives a gate line driving signal GOUTN−1 (or scan line driving signal) from a previous stage, and the present stage generates a gate line driving signal GOUTN.
In case that the present stage is the first stage of the shift register, the first stage receives a start signal STV generated from a timing controller (not shown), and the first stage generates a first gate line driving signal GOUT1. In case that the present stage is the second stage of the shift register, the second stage receives the first gate line driving signal GOUT1 generated from the first stage, and the second stage generates a second gate line driving signal GOUT2. Also, in case that the present stage is an Nth stage, the present stage receives an (N−1)th gate line driving signal GOUTN−1 generated from an (N−1)th stage, and the Nth stage generates an Nth gate line driving signal GOUTN. In like manner, the shift register having the N stages sequentially generates the gate line driving signals GOUT1, GOUT2, . . . , GOUTN.
The shift register also receives clock signals CKV and CKVB and voltage signals externally provided, and each stage of the shift register has multiple input terminals to receive those signals as well as other control signals and an output terminal to generate the corresponding gate line driving signal. A description of the overall operation of the shift register in FIG. 2 follows.
The first stage SRC1 receives the start signal STV generated from the timing controller (not shown), a gate turn-on voltage VON, a gate turn-off voltage VOFF, and a first clock signal CKV. The first stage SRC1 generates the first gate line driving signal GOUT1 for selecting a first gate line. The first gate line driving signal GOUT1 is provided to the first gate line and an input terminal (IN) of the second stage SRC2.
The second stage SRC2 receives the first gate line driving signal GOUT1 generated from the first stage SRC1, the gate turn-on voltage VON, the gate turn-off voltage VOFF, and a second clock signal CKVB. The second stage SRC2 generates the second gate line driving signal GOUT2 for selecting a second gate line. The second gate line driving signal GOUT2 is provided to the second gate line and an input terminal (IN) of the third stage SRC3.
Likewise, the Nth stage SRCN receives the (N−1)th gate line driving signal GOUTN−1 generated form the (N−1)th stage, the gate turn-on voltage VON, the gate turn-off voltage VOFF, and the second clock signal CKVB. The Nth stage SRCN generates the Nth gate line driving signal GOUTN for selecting an Nth gate line. The Nth gate line driving signal GOUTN is provided to the Nth gate line and an input terminal (IN) of the (N+1)th stage SRCN+1.
FIG. 3 is a timing diagram for describing the operation of the conventional shift register in FIGS. 1 and 2. Referring to FIGS. 1, 2 and 3, the shift register receives the first clock signal CKV and the second clock signal CKVB and sequentially outputs the gate line driving signals to the gate lines formed on a TFT substrate. The second clock signal CKVB has a 180° phase difference with respect to the first clock signal CKV. The amplitudes of the first and second clock signals CKV, CKVB are in a range from about −8 volt to about 24 volt. The amplitude of the output signal of the timing controller (not shown) is in a range from about 0 volt to about 3 volt. Thus, the output signal of the timing controller (not shown) is amplified so that the first and second clock signals CKV, CKVB have the amplitudes in the range from about −8 volt to about 24 volt.
Since the NMOS transistor Q1 of the pull-up part 110 includes amorphous-silicon, the NMOS transistor Q1 has a relatively large transistor size. This is because, in order to drive the liquid crystal display device having a large screen size, a large amplitude of voltage (for example, from −14V to 20V) should be applied to the NMOS transistor Q1 due to the very small electron mobility of the amorphous-silicon of the NMOS transistor Q1. For example, in a liquid crystal display panel having a screen size of 12.1 inch (XGA), parasitic capacitance of a gate line has a value from about 250 pF to about 300 pF. Therefore, in order to drive an amorphous-silicon thin film transistor designed in accordance with minimum design rule 4 μm, a channel width of the amorphous-silicon thin film transistor should be about 5500 μm when a channel length of the amorphous-silicon thin film transistor is about 4 μm.
Therefore, the parasitic capacitance between a gate electrode and a drain electrode of the NMOS amorphous-silicon thin film transistor Q1 increases. The value of the parasitic capacitance is about 3 pF. This value causes a malfunction of the gate driver circuit employing the NMOS amorphous-silicon thin film transistor. The malfunction occurs as follows.
The parasitic capacitor is electrically connected with a terminal to which the clock signal CKV or CKVB having a large amplitude of voltage (for example, from about −14V to about 20V) is applied, and the parasitic capacitor (or coupling capacitor) is electrically connected between the drain and gate electrodes of the NMOS amorphous-silicon thin film transistor Q1 to apply undesired voltage signal to the gate electrode of the NMOS amorphous-silicon thin film transistor Q1.
Assuming that there is no means for maintaining the voltage level of the gate electrode of the NMOS amorphous-silicon thin film transistor Q1 at the gate turn-off voltage level VOFF, the clock signal CKV or CKVB having the amplitude between about −14V and about 20V is applied to the gate electrode of the NMOS amorphous-silicon thin film transistor Q1. In this case, the voltage level of the gate electrode of the NMOS transistor Q1 becomes in the range from about −14V to about 20V, and the output signal equals to ‘20V (maximum value)−Vth (the threshold voltage of the NMOS amorphous-silicon transistor Q1)’. Applying such output signal to the gate line of the liquid crystal display panel causes abnormal display of images.
In order to maintain the voltage level of the gate electrode of the pull-up transistor Q1 at the gate turn-off voltage level VOFF, a hold transistor Q5 is employed. The hold transistor Q5 is an amorphous-silicon thin film transistor. Also, a pull-down thin film transistor Q2 performing a pull down function is employed to maintain the scan signal at the gate turn-off voltage level VOFF during most of the period after the pull-up transistor Q1 operates.
Since the a-Si transistor includes an N type MOSFET, the hold transistor Q5 receives a DC voltage signal proportional to the gate turn-on voltage VON (DC voltage signal) through the gate electrode of the hold transistor Q5 during the period except for the time period of ‘one vertical synchronization period—two horizontal synchronization periods’. In addition, the pull-down transistor Q2 receives a DC voltage signal proportional to the gate turn-on voltage VON (DC voltage signal) through the gate electrode of the pull-down transistor Q2 during the period except for the time period of ‘one vertical synchronization period—two horizontal synchronization period’. Hereinafter, one vertical synchronization period denotes a time interval between two consecutive frames. Namely, one vertical synchronization period is referred to as the time interval between the vertical synchronization signals (Vsync). The vertical synchronization signal (Vsync) indicates the point of time where a frame begins. One horizontal synchronization period denotes a time interval between two consecutive scan lines. Namely, one horizontal synchronization period is referred to as the time interval between the horizontal synchronization signals (Hsync). The horizontal synchronization signal (Hsync) indicates the point of time where a scan line of a frame begins.
When the gate driver integrated circuit employs a-Si transistors, the pull-down transistor Q2 and the hold transistor Q5 may be deteriorated since the DC voltage signal is applied to the gate electrodes of the pull-down transistor Q2 and the hold transistor Q5 for most of the operation period.
When DC voltage signal is continuously applied to the gate electrodes of the a-Si transistors (pull-down transistor Q2 and hold transistor Q5) for a predetermined period, the pull-down transistor Q2 and hold transistor Q5 are deteriorated, so that display quality of the liquid crystal display device becomes deteriorated. In other words, since the threshold voltages (Vth) of the a-Si transistors (pull-down transistor Q2 and hold transistor Q5) are increased due to the deterioration of the a-Si transistors, normal gate-source voltage Vgs becomes unable to turn on the a-Si transistors (pull-down transistor Q2 and hold transistor Q5) when the a-Si transistors (pull-down transistor Q2 and hold transistor Q5) have a predetermined threshold voltage Vth’.
FIG. 4 is a graph showing the variation of the threshold voltage of an a-Si TFT when a DC gate-source voltage is applied to the gate electrode of the a-Si TFT. As shown in FIG. 4, when a DC gate-source voltage is applied to the gate electrode of the a-Si TFT, the threshold voltage (Vth) of the a-Si transistor is increased due to the deterioration of the a-Si transistor. In case that the increased threshold voltage (Vth) reaches the DC gate-source voltage Vgs_dc, the a-Si transistor is not turned on even when a normal gate-source voltage Vgs is applied thereto.